1. Field of the Invention
The present invention relates to a mask ROM and a method for fabricating the same, and more particularly, to a mask ROM and a method for fabricating the same which is operative at a fast speed.
2. Background of the Related Art
Being a ROM for programming memory information in an integrated circuit fabrication process (a wafer process), the mask ROM can be written of a data only once, freely. As the mask ROM has no writing circuit, circuit is simple, as the mask ROM has a memory cell structure which requires no special process, the mask ROM is excellent in economy, the mask ROM has different memory cell systems applied to practice in different forms, the mask ROM is used differently according to purpose and use, and the mask ROM is featured in that a fabrication cost is the most economical inclusive of fabrication of a large size memory.
A related art method for fabricating a ROM will be explained with reference to the attached drawings. FIG. 1 illustrates a layout of a related art mask ROM, FIG. 2 illustrates a section across line I-I' in FIG. 1, and FIG. 3 illustrates a section across line II-II' in FIG. 1.
Referring to FIGS. 1.about.3, the related art mask ROM is provided with a semiconductor substrate 1 defined as a memory cell region A and a peripheral circuit region B; the memory cell region A is provided with first source and drain regions 2 and 3 formed in one direction at fixed intervals, and a plurality of wordlines 4 in a direction perpendicular to the direction of the first source and drain regions 2 and 3. The drain regions 3 are used as bitlines. And, the peripheral circuit region B is provided with gate electrode 5 in a direction the same with the direction of the first source and drain regions 2 and 3, and second source and drain regions 6 and 7 in the semiconductor substrate 1 on both sides of the gate electrode 5. There is a field oxide film 8 formed between the memory cell region A and the peripheral circuit region B, and the wordlines and the gate electrode 5 are insulated from the semiconductor substrate 1 by a gate oxide film 9 formed on the semiconductor substrate 1.
FIGS. 4a.about.4c illustrate layouts of FIG. 1 and sections across lines I-I' showing the steps of a fabricating method.
Referring to FIG. 4a, a field oxide film 8 is formed at an interface between a memory cell region A and a peripheral circuit region of a semiconductor substrate 1 which is defined as a memory cell region A and a peripheral circuit region B by general LOCOS(LOCal Oxidation of Silicon) process. Then, impurity ions of a conductivity opposite to a conductivity of the semiconductor substrate 1 in the memory cell region A are selectively injected into the memory cell region A, to form first source and drain regions 2 and 3 formed in one direction at fixed intervals. The drain regions 3 are used as bitlines. The peripheral circuit region B is not subjected to ion injection process for forming source and drain regions because the ion injection is done in self align after formation of the gate electrode (not shown). As shown in FIG. 4b, a gate oxide film 9 and a polysilicon layer are formed on an entire surface of the semiconductor substrate 1 inclusive of the field oxide film 8 in succession, wordline regions are defined, and the polysilicon layer is patterned (photolithography process+etching process) to leave the polysilicon only in the wordline region, to form a plurality of wordlines 4 crossed with the first source and drain regions 2 and 3. In this instance, the polysilicon layer on the peripheral circuit region B is also selectively patterned to form a gate electrode 5. The gate electrode 5 is patterned in a direction the same with the first source and drain regions 2 and 3. A resistivity per unit area of the wordline 4 of polysilicon is over approx. 6.about.7 .OMEGA./.quadrature.. In order to solve the problems of an increased RC (Resistance and Capacitance) delay and a large sized output terminal of a decoder which drives the wordlines both caused by a high density integration of the mask ROM, row decoder repeaters (not shown) are provided at intervals of the cells. The row decoder, corresponding to a length of approx. 1042(2.sup.10) cells, requires four of them if 4K.times.4K square array is provided, thereby solving the problems of the increased delay or the large sized decoder output terminal. And, as the source voltage is in a gradually lowered trend, such row decoder repeater becomes an essential element in a semiconductor device which requires high integration and a low voltage operation. As shown in FIG. 4c, impurity ions are injected into the semiconductor substrate on both sides of the gate electrode 5 in the peripheral region B, to form second source and drain regions 6 and 7. Though not shown in the drawing, in the process shown in FIG. 4a, an impurity ion injection process is conducted for an entire surface of the semiconductor substrate 1 for adjusting a cell threshold voltage before the impurity ion injection process for forming the first source and drain regions 2 and 3. The threshold voltage is adjusted to be approx. 0.7 v. Then, as shown in FIG. 4c, a code ion injection process is conducted according to a customer specification. Upon conduction of the ion injection, the threshold voltage of the cell becomes approx. 4.5 v. The aforementioned NOR type mask ROM is operative as a mask ROM by selection of a cell by the gate electrode 5 in the peripheral circuit region B, applying an appropriate value to the wordline 4, sensing the selected cell whether a code ion injected transistor or not, and determining a data. In this instance, in the code ion injection process, boron ions, impurity ions of a conductivity identical to a conductivity with the substrate (or a well if there is a well formed in the substrate), is injected for elevating the threshold voltage of a cell transistor from approx. 0.7 v to approx. 4.5 v, if the cell transistor is an NMOS (N type MOS).
However, the related art mask ROM and a method for fabricating the same have the following problems.
First, the row decoder repeater required for improving a wordline driving capability in an attempt to solve problems of a conductivity drop coming from an increased wordline length due to advanced integration increases a chip size.
Second, fabrication of a mask ROM which is operative at a low voltage and at a fast speed is difficult due to wordline length.
Third, the different source/drain region fabrication processes for the memory cell region and the peripheral circuit region results in a complicated fabrication processes, with a drop of productivity.